A high level modeling system (HLMS) is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS provides a higher level of abstraction for describing an electronic circuit than a hardware description language (HDL) simulation environment such as the ModelSim environment from the Model Technology company. An HLMS generally provides a mathematical representation of signals, as compared to standard logic vectors in a hardware description language (HDL). It is desirable for the high-level abstractions to be precisely correlated with the ultimate implementation representation, both in simulation semantics and in implementation. The System Generator tool for DSP (Sysgen) and ACCELDSP™ from XILINX, Inc., and SIMULINK® and MATLAB® environments from The MathWorks, Inc., are examples of such HLMSs.
An HLMS for electronic circuit design generally offers abstractions that are not available in traditional HDLs. For example, an HLMS is likely to offer abstractions that relate to signal propagation and signal state, while an HDL may support a detailed representation that more closely models a realized electronic circuit. An electronic design modeled in an HLMS may be viewed as a collection of components that communicate through signals. Signals are discrete, time-varying sequences of values. An HLMS generally provides abstractions to support implementing synchronous designs without requiring the specification of explicit references to clocks or clock signals. Instead of providing a detailed, event driven simulation, an HLMS may also provide abstractions wherein clock-synchronous state changes are scheduled to occur at regular intervals, and in which there is no notion of the timing characteristics related to the intended implementation as an electronic circuit. In further support of creating high-level designs, an HLMS may also represent states in terms of numerical (or other abstract) values instead of representing states in a detailed format analogous to standard logic vectors.
An HLMS such as Sysgen also has the capability to generate objects for co-simulating using a hardware platform. Co-simulation generally refers to dividing a design into portions and simulating the portions on two or more platforms. There are different types of platforms on which designs may be co-simulated.
Example co-simulation platforms include both software-based and hardware-based systems. The MODELSIM® simulation environment from Mentor Graphics Corp. and the NC-Sim simulator from Cadence Design Systems, Inc., are example software-based systems, and the Wildcard and BENONE® hardware-based platforms from Annapolis Microsystems and Nallatech, Inc., respectively, are example hardware-based systems. The WildCard and BENONE boards are often used for algorithm exploration and design prototyping, and include programmable logic devices (PLDs). In software-based co-simulations, the user may perform a behavioral simulation or perform simulation using a synthesized and mapped version of the design.
In a hardware-based system, a portion of the design is emulated on a hardware platform that includes a programmable logic device (PLD), such as a field programmable gate array (FPGA). Co-simulating on a hardware platform may be used to reduce the time required for a simulation run.
In a typical hardware-based co-simulation system, a hardware co-simulation interface (HWCIF) is combined with the portion of the design to be emulated (“hardware block”) on the PLD, for example. The HWCIF supports interactions between the parts of the design simulated in a software-based system and the hardware block. To facilitate lock-step simulations, the HWCIF also controls the clocking of the hardware block. The clock signal to the hardware block is temporarily gated off during the transmission of stimuli and results. When the transmission completes, a single or multiple clock cycle pulses are applied to the hardware block synchronous with the software simulation cycle.
In current hardware co-simulation systems the clock signal to the hardware block is controlled by the HWCIF, and the HWCIF may control stepping of the clock signal or allow the clock to run freely. In the step mode, the HWCIF issues an alternating bit pattern to produce a single cycle or a number of cycles for the clock signal to the hardware block. In the free running mode, the clock signal provided to the hardware block is generally the same as the clock signal used by the HWCIF.
The present invention addresses one or more issues in such co-simulation arrangements that may have been unrecognized.